Method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, device for encoding, signal comprising a stream of databits of a constrained binary channel signal, record carrier and device for decoding.
The invention relates to a method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, wherein the stream of databits of the binary information signal is divided into n-bit information words, said information words being converted into m1-bit channel words in accordance with a channel code C1, or m2-bit channel words, in accordance with a channel code C2, where m1, m2 and n are integers for which it holds that m2 greater than m1xe2x89xa7n, wherein the m2-bit channel word is chosen from at least two m2-bit channel words, at least two of which have opposite parities, the concatenated m1-bit channel words and the m2-bit channel words complying with a runlength constraint of the binary channel signal.
The invention also relates to a device for encoding a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal. The invention also relates to a signal comprising a stream of databits of a constrained binary channel signal. The invention further relates to a record carrier and to a device for decoding the constrained binary channel signal.
The invention is in the field of channel coding, in particular in runlength limited channel coding. The length of time, expressed in channel bits, between consecutive signal transitions is usually called the runlength. Different constraints can be imposed on a channel code, e.g. resulting in a runlength limited channel code. In such a code, a sequence of channel words is characterized by two parameters, a d-constraint and a k-constraint. In (d,k) domain a logical xe2x80x9conexe2x80x9d indicates a transition in the signal waveform. A (d,k) sequence satisfies the following two conditions: due to the d-constraint, two logic xe2x80x9conesxe2x80x9d are separated by a run of at least d consecutive xe2x80x9czeroesxe2x80x9d; due to the k-constraint two logic xe2x80x9conesxe2x80x9d are separated by a run of at most k consecutive xe2x80x9czeroesxe2x80x9d. The (d,k) sequence is converted from the (d,k) domain into a runlength-limited (RLL) sequence of the type (d,k) in the RLL domain upon precoding in a 1T precoder. This RLL sequence comprises elements with runlengths (either an array of consecutive zeroes or an array of consecutive ones) of d+1 at minimum and k+1 at maximum between subsequent signal reversals in the information signal. The values of (d+1) and (k+1) indicate the minimum and maximum runlengths of the element allowed in the sequence. It is noted that the term element can be used to indicate both an element of a (d,k) sequence or an element of an RLL sequence. An element is considered to be extending over a runlength in the RLL domain or (d,k) domain.
In runlength limited channel coding, each information word is converted into a channel word according to predefined rules of conversion, these channel words forming a modulated signal.
Research Disclosure, January 1992, page 32, 33340, discloses a coding method according to which n-bit information words are alternately converted into m1-bit channel words and m2-bit channel words, where n, m1 and m2 are integers and nxe2x89xa6m1 less than m2. For each n-bit information word, there are two m2-bit channel words available having mutually different disparities. A channel word is selected so that the current running digital sum in the channel signal shows a behaviour in accordance with a desired pattern as a function of time, for example a DC-free coding in the channel signal.
In other words, there are two channel codes involved in the Research Disclosure, one with an n-to-m1 mapping of information words into channel words, which can be referred to as the main code C1, and the other with an n-to-m2 mapping, with two m2-bit channel words, which can be referred to as the dual code C2.
The efficiency of a channel code can be expressed by using the (information) rate of the channel code. This rate R of a channel code is defined as the quotient n/m, in which the code translated n binary user (or information) symbols into m binary channel symbols. As explained above, in runlength limited channel coding, the channel words must comply with certain constraints, for example a d-constraint and a k-constraint. Due to these restrictions, the number of bit combinations which may represent the information words is lowered and therefore the rate will decrease.
It is an object of the invention to realize an efficient method of encoding a stream of information words into a constrained stream of channel words.
The method in accordance with the invention is characterized in that the method comprises the repetitive and/or alternate steps of:
selecting the m1-bit channel word from a set out of a plurality of sets of m1-bit channel words, each set comprising only m1-bit channel words having a beginning part out of a subset of beginning parts of the m1-bit channel words, each set being associated with a coding state of channel code C1, the coding state being established in dependence upon an end part of the preceding channel word,
or:
selecting the m2-bit channel word from a set out of a plurality of sets of m2-bit channel words, each set comprising only m2-bit channel words having a beginning part out of a subset of beginning parts of the m2-bit channel words belonging to said set, each set being associated with a coding state of channel code C2, the coding state being established in dependence upon an end part of the preceding channel word,
the end parts of the m1-bit channel words in a coding state of channel code C1 and the beginning parts of the m2-bit channel words in a set of channel code C2 being arranged to comply with said runlength constraint.
By repetitively or alternately performing said steps and by arranging the end parts of the m1-bit channel words in a coding state of channel code C1 and the beginning parts of the m2-bit channel words in a coding state of channel code C2, the beginning parts of the m2-bit channel words can be applied to the coding states of channel code C1, thereby realizing the constrained binary channel signal; and vice versa when arranging the end parts of the m2-bit channel words and the beginning parts of the m1-bit channel words.
The invention is based on the recognition that the coding states of two different channel codes can be combined by arranging the beginning parts and the end parts of the channel words of the channel codes, so that end parts in the channel code C1 match with beginning parts of the sets of m1-bit channel words, but also with the beginning parts of the sets of m2-bit channel words. A multiple-state description of encoder and decoder yields channel codes with high efficiency or information rate.
Another method according to the invention is characterized in that the number of coding states of channel code C1 is equal to the number of coding states of channel code C2.
In the case where for the dual code C2, two m2-bit channel words with opposite parity can be used for each n-bit information word, it is possible to use these channel words for influencing predetermined properties of the binary channel signal. In order to be able to comply with the constraints of the constrained stream of channel words, it is advantageous that the end parts of the m1-bit channel words in a coding state of channel code C1 and the beginning parts of the m2-bit channel words in a coding state of channel code C2 are arranged that the number of coding states of channel code C1 is equal to the number of coding states of channel code C2. In this way, the coding tables can be limited. Parts of the coding states of channel code C1 can for example be similar or equal to parts of the coding states of channel code C2. This results in an easier implementation of coding and decoding in hardware and/or software.
The channel codes according to the invention may be uniquely described in terms of a so-called finite-state-machine (FSM). Transitions between the states of the FSM correspond to the emission of channel words in accordance with n-bit information words that enter the encoder. This implies thatxe2x80x94in order to have a valid codexe2x80x94from each state of the FSM, there must be leaving at least 2n transitions towards all states of the FSM. With the FSM being in a given state, a given n-bit information word does not only determine the m-bit channel words, but also the next-state from which the next n-bit information word entering the encoder, is to be encoded.
Another method according to the invention is characterized in that the end part of any m1-bit channel word has a multiplicity y1, the multiplicity y1 being the number of different states of the channel code C1 said end part may establish, and that the end part of any m2-bit channel word has a multiplicity y2, the multiplicity y2 being the number of states of the channel code C2 said end may establish and in that y1=y2 if the end part of the m1-bit channel word is equal to the end part of the m2-bit channel word.
Each end part of the m1-bit channel word has a multiplicity y1, the multiplicity y1 being the number of states of the channel code C1 said end part is permitted in, and each end part of the m2-bit channel word has a multiplicity y2, the multiplicity y2 being the number of states of the channel code C2 said end part is permitted in. It is not necessary that the multiplicity of an end part of a word is used for 100%. It is advantageous that y1=y2, if the end part of the m1-bit channel word is equal to the end part of the m2-bit channel word. In this way the coding states of channel code C1 and the coding states of channel code C2 can be alternated in order that the constrained binary channel signal, comprising the concatenated m1-bit channel words and the m2-bit channel words, obeys a constraint of the binary channel signal. Using an equal multiplicity results in an easier implementation of coding and decoding in hardware and/or software.
Another method according to the invention is characterized in that said at least two m2-bit channel words establish the same state.
We have so far defined the dual code C2 as having the following properties: it is a code with n-to-m2 mapping, where each n-bit information word can be represented by at least two channel words, among which at least two have opposite parities. The latter property is intended for influencing some envisaged properties of the encoded channel bitstream, e.g. control of the DC-content of the code.
However, the guaranteed parity selection property of the dual code C2 is not satisfactory to guarantee, for instance a DC-control of a predetermined performance level. This is due to the fact that, in the FSM, both channel words of the dual code C2 may lead to different next-states: this would imply that the subsequent encoding paths for the two distinct choices of the channel words of C2 may be completely different, and that the overall parity of the bitstream between the two channel words encoded with the dual code, can be different, so that the DC-control which is driven by the decisions of the words of the dual code C2, gets frustrated, leading to a potentially poor performance with respect to the desired property of the channel bitstream.
It is therefore advantageous to design the states of the FSMs of the channel codes C1 and C2 in order that, upon converting an n-bit information word into the two m2-bit channel words, the two m2-bit channel words not only leave from the same state in the FSM but also end in the same next-state in the FSM. In other words, both channel words of C2, corresponding to the same n-bit information word, have the same next-state. The use of this so-called xe2x80x9csame-next-statexe2x80x9d property of the dual code C2 leads to the following advantage: the above frustration of the control via C2 is eliminated: the encoding paths of the main code C1 between successive points where C2 is used in the stream of information words is now completely fixed, thus implying the same parity of the channel bitstream encoded with C1 between successive locations where C2 is used, independent of the coding choices of C2.
Having a choice between the two m2-bit channel words, enables performing DC-control in order to achieve a so-called DC-balanced or a DC-free code. E.g. in optical recording, DC-balanced codes are employed to circumvent or reduce interaction between the data written on a record carrier and the servosystems that follow a track on the record carrier. The bytes encoded with the dual code C2 are the points in the channel bitstream that allow for control of the DC-content. Apart from controlling the DC-content of the channel bitstream the bytes encoded with the dual code C2 can be used for influencing other properties of the channel bitstream.
Straightforward DC-control procedures make a decision at each DC-control point depending on an RDS-related criterion, which is evaluated only for the channel bitstream ranging from the considered DC-control point up to the next one. Such locally optimal decision strategy does not exploit all DC-control potential of the channel code. A better approach is to apply look-ahead DC-control, i.e. to build a decision tree of depth N in which the decision at a given DC-control point is determined also by its impact on the subsequent channel bitstream in combination with the future decisions at the next N-1 DC-control points. Each path through the decision tree consists of N branches, and the RDS-criterion applies for the complete path. N-fold Look-Ahead DC-control implies 2N encoding paths, with the drawback of a higher encoder complexity since each byte needs to be encoded 2N times.
For the channel code according to this embodiment, the path followed through the FSM during encoding does not depend on the actual path followed through the N-fold decision tree. This is due to the xe2x80x9csame-next-statexe2x80x9d property of the two coding options at the dual code C2. Hence, all bytes related to the main code C1, need to be encoded only once, whereas all bytes related to the dual code C2, need to be encoded just twice. This reduces the hardware complexity of the encoding tree down to that related to a simple sequential encoding without further branching. Only the N-fold decision tree of RDS-criteria along the 2N paths remains, resulting in a lower complexity.
An RDS-related criterion can be, for example, the maximum absolute value of the RDS-value itself (first order spectral zero), but also the integrated RDS-value in time (second order spectral zero) or a combination of both can be used. Also the sum variance (SV) can be used as a criterion.
Another method according to the invention is characterized in that the sets of channel words of channel code C1 and the coding states of channel code C2 are arranged that binary channel signal formed by the concatenated m1-bit channel words and the m2-bit channel words comply with a Repeated-Minimum-Runlength-Limitation=6 constraint on the binary channel.
Constraints can also limit the number of consecutive runlengths of the same length. For example, when imposing an RMTR (Repeated Minimum Transition Runlength) constraint of n on a d=2 channel code, this constraint implies that the number of successive 3T runlengths in the sequence of channel words is limited to n. In order to realize a Repeated-Minimum-Runlength-Limitation of 6 constraint, code tables are designed from which possible channel words that could lead to the violation of the RMTR-constraint are eliminated (e.g. the word (100)5). In another way, the RMTR-constraint can also be obeyed by substituting channel words or patterns when an RMTR-violation would take place. More information about this RMTR (Repeated Minimum Transition Runlength) constraint can be found in published patent application WO99/63671-A1 (PHQ 98.023).
Another method according to the invention is characterized in that the ratio between the number of m1-bit channel words and the number of m2-bit channel words is determined in dependence of a chosen measure of DC-control.
It should be noted that the two channel codes C1 and C2 are independent codes each, which can also be used separately. C1 is typically a high-rate code with no systematic structure to steer certain extra properties of the encoded channel bitstream on top of the envisaged runlength constraints (d, k, RMTR). C2 is a slightly lower-rate code and the rate-loss as compared to C1, is used for a systematic structure aimed at steering the additionally required properties. For the invention as described in detail below, C1 and C2 are to be used in combination, from which the term combi-code is derived, but it should be realized that any combination pattern is possible. The more the main code C1 is used (relative to the use of the dual code C2), the higher the rate will be of the overall combination code, but also the lower the controlling capacity will be for the extra envisaged properties of the channel bitstream. With respect to the latter, a maximum of control can be achieved by using the dual code C2 all the time, and a minimum of control is the case when using only the main code C1. It can therefore be understood that the ratio between the number of m1-bit channel words and the number of m2-bit channel words can be determined in dependence upon a chosen measure of DC-control.
Another method according to the invention is characterized in that the coding state is further being established in dependence upon the n-bit information word, thereby allowing to distinguish this n-bit information word by detecting the coding state.
In order to increase the rate of the information signal, it is advantageous that the coding state is also dependent on the n-bit information word to be encoded. As a result, the same channel word can be used more than one time. In this way, the number of different channel words necessary to construct a channel code is reduced, resulting in a more efficient code. Using states in the framework of a so-called finite-state-machine (FSM) for the characterization of the channel codes C1 and C2, therefore provides a possibility of establishing an overall code with a high rate due to the multiple use of the same channel word with different next-states. At the decoder, it is the channel word in combination with the next-state, that uniquely determines the corresponding information word.
Another method according to the invention is characterized in that the coding states of channel code C1 and the coding states of channel code C2 are further arranged that a limited number of channel words is substituted for other channel words or patterns, these other channel words or patterns not belonging to the sets of channel words of channel code C1 and channel code C2.
In a practical design of a channel code based on the combination of two codes C1 and C2 according to the invention, there is some extra room for the design of limited, stochastic control on top of the guaranteed control. Stochastic control is understood to be the kind of control in which the actual use of this control depends on the actual data content (information words) that enters the encoder.
The existence of the room for stochastic DC-control is due to the fact thatxe2x80x94in a practical codexe2x80x94some specific patterns do not occur in the channel bitstream under normal application of the channel code; these patterns can then be used as substitution patterns for other patterns that are allowed in the channel bitstream.
By substituting a limited number of channel words or patterns for other channel words or patterns not belonging to the channel words or patterns present in the binary channel signal before the substitutions, additional DC-control can be accomplished, for instance, if the substitutions imply a parity inversion.
The coding methods as described in the above embodiments have the following advantages, which are obvious or will be clarified in the Figure description, i) guaranteed DC-control, ii) reduced error-propagation because of the byte-oriented nature of the encoding, iii) simple single-pass encoding scheme, resulting in reduced encoder complexity for performing encoding with look-ahead DC-control.
The invention also relates to a device for encoding. The invention also relates to a signal comprising a stream of databits of a constrained binary channel signal. The invention further relates to a record carrier and to a device for decoding.